module top_module (
    input clk,
    input reset,
    output [9:0] q);

	reg[9:0]cout;
	always@(posedge clk)begin
		if(reset)begin
			cout<=10'h0;
		end
		else begin
			if(cout<10'h3e7)
				cout<=cout+10'h1;
			else
				cout<=10'h0;
		end
	end
	assign q=cout;
endmodule